1. Field of the Invention
The present invention relates to a plating method and a plating apparatus, and more particularly to a plating method and a plating apparatus which are useful for forming a protective film by electroless plating selectively on the exposed surfaces of embedded interconnects of an interconnect material, such as copper or silver, embedded in interconnect recesses provided in the surface of a substrate, such as a semiconductor wafer, so as to cover and protect the interconnects with the protective film.
The present invention also relates to an interconnects-forming method useful for forming embedded interconnects by embedding an interconnect material, such as copper or silver, in interconnect recesses provided in a surface of a substrate, such as a semiconductor wafer, and covering the surfaces of the embedded interconnects with a protective film to make a multi-level structure.
2. Description of the Related Art
As a process for forming interconnects in a semiconductor substrate, a so-called “damascene process”, which comprises embedding an interconnect material (metal) into trenches and via holes, is coming into practical use. According to this process, aluminum, or more recently an interconnect material (metal) such as silver or copper, is embedded into interconnect recesses, such as trenches and via holes, previously formed in an interlevel dielectric layer. Thereafter, an extra metal is removed by performing chemical-mechanical polishing (CMP) so as to flatten a surface of the substrate.
In a case of interconnects formed by such a process, for example, copper interconnects formed by using copper as an interconnect material, embedded interconnects of copper have exposed surfaces after the flattening processing. In order to prevent thermal diffusion of such interconnects (copper), or to prevent oxidation of such interconnects (copper) e.g. during forming thereon an insulating film (oxide film) under an oxidizing atmosphere to produce a semiconductor substrate having a multi-layer interconnect structure, it is now under study to selectively cover the exposed surfaces of interconnects with an protective film (cap material) composed of a Co alloy, a Ni alloy or the like so as to prevent thermal diffusion and oxidation of the interconnects. Such an protective film of a Co alloy, a Ni alloy or the like can be produced e.g. by performing electroless plating.
FIGS. 1A through 1D illustrate, in sequence of process steps, an example of forming copper interconnects in a semiconductor device. As shown in FIG. 1A, an insulating film (interlevel dielectric layer) 2, such as an oxide film of SiO2 or a film of low-k material, is deposited on a conductive layer 1a formed on a semiconductor base 1 having formed semiconductor devices. Via holes 3 and trenches 4 are formed in the insulating film 2 by performing a lithography/etching technique so as to provide interconnect recesses. Thereafter, a barrier layer 5 of TaN or the like is formed on the insulating film 2, and a seed layer 6 as a feeding layer for electroplating is formed on the barrier layer 5 by sputtering or the like.
Then, as shown in FIG. 1B, copper plating is performed on a surface of a substrate W to fill the via holes 3 and the trenches 4 of the substrate W with copper and, at the same time, deposit a copper film 7 on the insulating film 2. Thereafter, the barrier layer 5, the seed layer 6 and the copper film 7 on the insulating film 2 are removed by chemical-mechanical polishing (CMP) or the like so as to leave copper filled in the via holes 3 and the trenches 4, and have a surface of the insulating film 2 lie substantially on the same plane as this copper. Interconnects (copper interconnects) 8 composed of the seed layer 6 and the copper film 7 are thus formed in the insulating film 2, as shown in FIG. 1C.
Then, as shown in FIG. 1D, electroless plating is performed on a surface of the substrate W to selectively form a protective film 9 of a Co alloy, a Ni alloy or the like on surfaces of the interconnects 8, thereby covering and protecting the surfaces of the interconnects 8 with the protective film 9.
There will be described a process of forming a protective film (cap material) 9 of, for example, a CoWP alloy film selectively on surfaces of interconnects 8 by using a general electroless plating method. First, a substrate such as a semiconductor wafer after CMP processing is immersed in e.g. an aqueous H2SO4 solution to etch away e.g. copper oxide on interconnects 8, thereby activating surfaces of interconnects 8. After the surface of the substrate W is cleaned with a cleaning liquid such as pure water, if necessary, the substrate W is immersed, for example, in a PdCl2/HCl mixed solution to adhere Pd as a catalyst to the surfaces of the interconnects 8. After the surface of the substrate W is cleaned (rinsed) with pure water or the like, the substrate W is immersed, for example, in a CoWP plating solution to carry out electroless plating selectively on surfaces of the Pd adhered interconnects 8. Thereafter, the surface of the substrate W is cleaned with a cleaning liquid such as pure water. Thus, a protective film 9 made of a CoWP alloy film is formed selectively on the exposed surfaces of interconnects 8 so as to protect interconnects 8.
The application of a catalyst such as Pd, in principle, is effected through a displacement reaction caused by electrons (e−) that are emitted from interconnects (base metal) upon etching thereof, i.e. through the so-called “displacement plating”. The catalyst application involves the problem that interconnects as a base metal can be etched excessively especially at weak crystal grain boundaries. The excessive etching in interconnects may result in the formation of voids in the interconnects, which would lower the reliability of the interconnects and increase the resistance of the interconnects. This has led to difficulty in establishing a practical process.
This problem will be explained taking as an example the case of forming a copper film 502, constituting interconnects 8 (see FIG. 1C), on the surface of a barrier layer 500 of TaN, and forming a protective film 504 of a CoWP alloy on the surface of the copper film 502 by electroless plating, as schematically shown in FIGS. 2A through 2D.
The copper film 502 is a polycrystalline film having a plurality of crystalline orientations and comprising a large number of copper crystal grains 502a which are considered to be linked planewise to each other at crystal grain boundaries 502b, as shown in FIG. 2A. The surface of the copper film 502 is immersed in e.g. an aqueous H2SO4 solution to etch away copper oxide (CuO) present in the surface of the copper film 502 with H2SO4, thereby activating the surface, as shown by the following formula (1). Upon the etching, as shown in FIG. 2B, the copper film 502 is etched and removed excessively at the upper portions of the crystal grain boundaries 502b between adjacent copper crystal grains 502a, resulting in the formation of recesses 506.CuO+H2SO4→CuSO4+H2O  (1)
When the surface of the copper film 502 is subsequently immersed in e.g. a PdSO4/H2SO4 mixed solution to form a Pd catalyst layer 508, comprising Pd as a catalyst, on the surface of the copper film 502, copper is etched excessively along the weak crystal grain boundaries 502 especially and electrons are emitted from the copper, as shown by the following formula (2). At the surfaces of the copper crystal grains 502a, Pd2+ ions receive the electrons whereby the Pd catalyst layer is formed, as shown by the following formula (3). The additional excessive etching of copper along the crystal grain boundaries 502b results in the formation of voids 510, as shown in FIG. 2C.Cu→Cu2++2e−  (2)Pd2++2e−→Pd  (3)
When a protective film 504 of a CoWP alloy is subsequently formed by electroless plating on the surface of the copper film 502, the voids 510 remain within the copper film (interconnects) 502 covered with the protective film 504. Further, in principle, a liquid remains in the voids 510. Upon a heat treatment which is necessary for the production of interconnects, the liquid remaining in the voids 510 will expand, leading to the growth of the voids 510.
The application of a catalyst such as Pd to a copper surface is requisite for forming a CoWP alloy film on the copper surface by electroless plating. A CoWP alloy film is in no case deposited directly on a copper surface by electroless plating.
There is a case where upon the formation of a protective film by electroless plating onto interconnects of a substrate after removal of an extra metal on the substrate and flattening of the substrate surface by CMP, the pattern dependency of the interconnects and the protective film associated with the rate limitation of the supply of reaction species, becomes marked whereby the thickness of the protective film formed selectively on the surfaces of the interconnects by electroless plating becomes uneven. This may lead to a failure in obtaining a stable interconnects-forming process and a lowering of the throughput.
In particular, upon the selective formation of a protective film on interconnects by electroless plating, a thickness of the protective film is likely to vary due to a variation in the density of the interconnects. Such an uneven film cannot fully function as a protective film. Further, especially for an isolated narrow interconnect pattern, there may exist a transition time until the initiation of plating reaction, whereby the plating cannot be deposited with ease.
Consider now a case where a first interconnect pattern, for example, comprising isolated interconnects (narrow interconnects) 8 having a width of 0.25 μm arranged at intervals of 10 μm as shown in FIG. 3A, a second interconnect pattern, for example, comprising interconnects (narrow interconnects) 8 having a width of 0.25 μm density arranged at intervals of 0.25 μm as shown in FIG. 3B, and a third interconnect pattern, for example, comprising isolated interconnects (broad interconnects) 8 having a width of 10 μm arranged at intervals of 1 μm as shown in FIG. 3C, are co-present in a surface of a substrate.
Polishing and removal of copper by CMP is generally carried out by oxidizing the copper and polishing away the copper oxide. Accordingly, when the above substrate having a variety of interconnect patterns is subjected to the above-described process comprising embedding of copper as an interconnect material, followed by CMP to remove an unnecessary metal on an insulating film and flatten the surface, oxide films 8a are formed in the upper portions of the interconnects 8 which are formed in trenches 4, covered with a barrier layer 5, provided in an insulating film 2, as shown in FIGS. 3A through 3C. The thickness of the respective oxides 8a of the various interconnect patterns differ from one another due to a difference in reaction produced by the rate limitation of the supply of reaction species. In particular, a relatively thick oxide film 8a having a thickness of e.g. about 10 nm is formed in the first interconnect pattern, as shown in FIG. 3A. An oxide film 8a having an intermediate thickness of e.g. about 6 nm is formed in the second interconnect pattern, as shown in FIG. 3B. And in the third interconnect pattern, a relatively thin oxide film 8a having a thickness of e.g. about 4 nm is formed, as shown in FIG. 3C.
When the substrate is subjected to a pre-electroless plating treatment to remove the oxide films 8a formed in the upper portions of interconnects 8, spaces 10 having heights equal to the thicknesses of the corresponding oxide films 8a removed are formed in the trenches 4, as shown in FIGS. 4A through 4C. Thus, a space 10 having a height of e.g. about 10 nm is formed in the first interconnect pattern, as shown in FIG. 4A. A space 10 having a height of e.g. about 6 nm is formed in the second interconnect pattern, as shown in FIG. 4B. And in the third interconnect pattern, a space 10 having a height of e.g. 4 nm is formed, as shown in FIG. 4C.
When the substrate is subsequently subjected to electroless plating to form a protective film 9 of e.g. a NiB alloy selectively on the surfaces of the interconnects 8, the thickness of the protective film 9 varies depending on the interconnect pattern configuration, due to a difference in reaction produced by the rate limitation of the supply of reaction species, as shown in FIGS. 5A through 5C. In particular, a protective film 9 having a thickness of e.g. about 10 nm (FIG. 5A) is formed in the first interconnect pattern. A protective film 9 having a thickness of e.g. about 6 nm (FIG. 5B) is formed in the second interconnect pattern. And in the third interconnect pattern, a protective film 9 having a thickness of e.g. about 4 nm (FIG. 5C) is formed. As in this case, the narrower and the more isolated interconnects are, a protective film formed on the exposed surfaces of interconnects tends to be thicker.
The interconnect pattern dependency of the thickness of a protective film is due to a difference in reaction produced by the rate limitation of the supply of reaction species. In particular, for an interconnect pattern comprising a single interconnect (reaction region) 8 having a surface area of 2×10 in a region (surface area) of 10×10, as shown in FIG. 6A, the ratio of the reaction region to the whole region is 0.2 (20/100). For an interconnect pattern comprising two interconnects (reaction regions) each having a surface area of 2×10 in a region of 10×10, as shown in FIG. 6B, the ratio of the reaction regions to the whole region is 0.4 (2×20/100). Further, for an interconnect pattern comprising a single interconnect (reaction region) 8 having a surface area of 5.2×10 in a region of 10×10, as shown in FIG. 6C, the ratio of the reaction region to the whole region is 0.52 (52/100). Thus, the larger the ratio of the reaction region (area) to the whole region (area) is, the thinner oxide film 8a is formed in the upper portions of interconnects 8 upon CMP, resulting in the formation of a thinner protective film 9.
Further, an insulating film (interlevel dielectric layer), for example composed of SiO2, surrounding embedded interconnects generally has a poor thermal conductivity. In addition, the plating rate in electroless plating is influenced largely by a temperature factor. FIG. 7 shows the relationship between the plating rate and the liquid temperature of plating solution in electroless CoWB plating. As can be seen from FIG. 7, the plating deposition is impossible at the liquid temperature of 52° C. or lower and, in the liquid temperature range of 55-70° C., the temperature difference of 1° C. produces a difference of about 1.3 nm/min in the plating rate.
Accordingly, when a substrate, after carrying out the pre-plating treatment shown in FIGS. 4A through 4C, is subjected to electroless plating, for example, using an electroless CoWB plating solution at a liquid temperature of 60° C. to form a protective film 9 of a CoWB alloy on the surfaces of interconnects 8, a relatively thin protective film 9 is formed in the first interconnect pattern, as shown in FIG. 8A. A relatively thick protective film 9 is formed in the second interconnect pattern, as shown in FIG. 8B. And in the third interconnect pattern, a protective film 9 having an intermediate thickness is formed, as shown in FIG. 8C. Thus, the narrower and the more isolated interconnects are, a protective film formed on the exposed surfaces of interconnects tends to be thinner due to a shortage of heat capacity.